Verilator: FLOSS tool for converting Verilog to a cycle-accurate behaviour model in C++ or SystemC. VASG: VHDL Analysis and Standardization Group (see /cgi-bin/view.cgi/P1076). QEMU: a generic and open source machine emulator and virtualizer. PSL: Property Specification Language, IEEE Std 1850, incorporated in IEEE Std 1076-2008 (see Wikipedia: Property Specification Language). PPC: commonly used to refer to PowerPC and/or Power ISA processors. PLI was superseeded by VPI in IEEE Std 1364-2005, sometimes referred to as PLI 2.
#MODELSIM WIKI VERIFICATION#
OSVVM: Open Source VHDL Verification Methodology. LLVM: a compiler infrastructure designed around a language-independent IR. IEEE: Institute of Electrical and Electronics Engineers (see ). GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. Mentor Graphics’ ModelSim/ Questa tools implement an interface named VHDL FLI: “ FLI routines are C programming language functions that provide procedural access to information within Model Technology’s HDL simulator, vsim”.įOSS/FLOSS: Free/Libre and Open Source Software. SystemVerilog DPI is an interface which can be used to interface SystemVerilog with foreign languages (see Wikipedia: SystemVerilog DPI).įFI: Foreign Function Interface, a mechanism by which a program written in one programming language can call routines or make use of services written in another (see Wikipedia: Foreign function interface).įIFO: First In First Out, a method for organising the manipulation of a data structure where the oldest (first) entry, or head of the queue, is processed first (see Wikipedia: FIFO (computing and electronics)).įLI: Foreign Language Interface. 4.8 Providing custom(izable) GUI interfaces to interact with simulations at runtimeĪPI: Application Programming Interface (see Wikipedia: Application programming interface).ĪBI: Application Binary Interface (see Wikipedia: Application binary interface).Ĭocotb: a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
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3.3 Deferred definition of external subprograms.
#MODELSIM WIKI REGISTRATION#